PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 262

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Errored Second Mask (Read/Write)
Value after reset: FF
ESM
ESM
Disable Error Counter (Write)
Value after reset: 00
DEC
DRBD
DCEC3
DCEC2
DCEC1
DEBC
DCVC
DFEC
Note: Error counters and receive buffer delay can be read 1 µs after setting the
Data Sheet
according bit in bit DEC.
DRBD
LFA
7
7
Errored Second Mask
This register functions as an additional mask register for the interrupt
status bit Errored Second (ISR3.ES). A "1" in a bit position of ESM
deactivates the related second interrupt.
Disable Receive Buffer Delay
This bit has to be set before reading the register RBD. It is reset
automatically if RBD has been read.
Disable CRC Error Counter 3
Disable CRC Error Counter 2
Disable CRC Error Counter
Disable Errored Block Counter
Disable Code Violation Counter
Disable Framing Error Counter
These bits are only valid if FMR1.ECM is cleared. They have to be set
before reading the error counters. They are reset automatically if the
corresponding error counter high byte has been read. With the rising
edge of these bits the error counters are latched and then cleared.
FER
H
H
DCEC3 DCEC2 DCEC1
CER
AIS
262
LOS
DEBC
CVE
DCVC
SLIP
DFEC
FALC56 V1.2
EBE
E1 Registers
0
0
PEB 2256
2002-08-27
(47)
(60)