PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 131

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

The 24 received time slots (T1/J1) can be translated into the 32 system time slots (E1)
in two different channel translation modes (FMR1.CTM). Unequipped time slots are set
to FF
Table 30
– : FF
In one frame or short buffer mode the delay through the receive buffer is reduced to an
average delay of 96 or 48 bits. In bypass mode the time slot assigner is disabled. In this
case SYPR programmed as input is ignored. Slips are performed in all buffer modes
except the bypass mode. After a slip is detected the read pointer is adjusted to one half
of the current buffer size.
The following table gives an overview of the receive buffer operating mode.
Data Sheet
Translation
Channel
Mode 0
FS/DL
H
H
10
11
12
. See
1
2
3
–
4
5
6
–
7
8
9
–
Channels
Table
Channel Translation Modes (DS1/J1)
Translation
Channel
Mode 1
FS/DL
30.
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
Time Slots
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
131
Translation
Channel
Mode 0
13
14
15
16
17
18
19
20
21
22
23
24
–
–
–
–
Channels
Functional Description T1/J1
Translation
Channel
Mode 1
16
17
18
19
20
21
22
23
24
–
–
–
–
–
–
–
FALC56 V1.2
Time Slots
PEB 2256
2002-08-27
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31