PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 355

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

SSC2
Transmit Control 0 (Read/Write)
Value after reset: 00
XC0
BRM
MFBS
BRFO
XCO(10:8)
Data Sheet
BRM
7
Select Sync Conditions
Only valid in ESF framing format.
Loss of Frame Alignment FRS0.LFA is declared if more than 320
CRC6 errors per second interval are detected.
Enable Bit Robbing Marker
A one in this bit marks the robbed bit positions on the system highway.
RSIGM marks the receive and XSIGM marks the transmit robbed bits.
Enable pure Multiframe Begin Signals
Only valid if ESF or F72 format is selected.
0 =
1 =
Bit Robbing Force One
Setting this bit forces the robbed bits high transmitted on port RDO.
The received signaling data stream for the signaling controller is not
influenced by this bit.
Transmit Offset
Initial value loaded into the transmit bit counter at the trigger edge of
SCLKX when the synchronous pulse on port SYPX or XMFS is active
Refer to register XC1.
MFBS
H
selected. For proper operation the transmit elastic buffer (2
frames, SIC1.XBS(1:0) = 10) has to be enabled.
RMFB marks the beginning of every received superframe.
Additional pulses are provided every 12 frames when using
ESF/F24 or F72 format.
RMFB marks the beginning of every received multiframe.
355
BRFO
XCO10
XCO9
T1/J1 Registers
XCO8
FALC56 V1.2
0
PEB 2256
2002-08-27
(22)