s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 200

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

SYSTEM MANAGER
Relationship Between CAN (Column Address Number) and Address MUX Output for SDRAM
NOTES:
1.
2.
DRAM BANK SPACE
The S3C4510B DRAM interface supports four DRAM banks. Each bank can have a different configuration. You
use the DRAM control registers, DRAMCON0-DRAMCON3, to program the DRAM access cycles and memory
bank locations.
Each DRAM control register has two 10-bit address pointers, one base pointer and one next pointer, to denote the
start and end address of each DRAM bank. The 10-bit pointer values are mapped to the address [25:16]. This
gives each bank address an offset value of 64 K bytes (16 bits). The next pointer value will be the DRAM bank's
end address + 1.
System Initialization Values
When the system is initialized, the four DRAM control registers are initialized to 00000000H, disabling all external
DRAMs.
4-58
CAN
A22 to A0 depends on external bus width. In case of x32 memory, A[22:0] is word address.
A[22:0] consists of: Bank Address + Valid Row Address + Valid Column Address
00
01
10
address
address
address
address
address
address
Timing
Column
Column
Column
Output
Row
Row
Row
[21:15]
x
x
x
x
x
x
Table 4-23. CAN and Address MUX Output
A22
A22
14
0
0
0
0
A21
A21
A22
A22
13
0
0
External Address Pins (ADDR)
A20
A20
A21
A21
A22
A22
12
A19
A19
A20
A20
A21
A21
11
A10/AP
A10/AP
A10/AP
A18
A19
A20
10
A17
A18
A19
A9
A9
A9
9
A16
A17
A18
A8
A8
A8
8
A17-A10
S3C4510B
A15-A8
A16-A9
A7-A0
A7-A0
A7-A0
7-0