s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 288

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s3c4510b

Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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HDLC CONTROLLERS
FEATURES
Important features of the S3C4510B HDLC block are as follows:
— Protocol features:
— Four address station registers and one mask register for address search mode
— Selectable CRC/No-CRC mode
— Automatic CRC generator preset
— Digital PLL block for clock recovery
— Baud rate generator
— NRZ/NRZI/FM/Manchester data formats for Tx/Rx
— Loop-back and auto-echo mode
— Tx and Rx clock inversion
— Tx and Rx FIFOs with 8-word (8 x 32-bit) depth
— Selectable 1-word or 4-word data transfer mode for Tx/Rx
— Data alignment logic
— Endian translation
— Programmable interrupts
— Modem interface
— Hardware flow control
— Buffer descriptor for Tx / Rx
— Two-channel DMA Controller
— Up to 10 Mbps full-duplex operation using an external/internal clock
— HDLC frame length based on octets
8-2
Flag detection and synchronization
Zero insertion and deletion
Idle detection and transmission
FCS encoding and detection (16-bit)
Abort detection and transmission
Two channels for HTxFIFO and HRXFIFO
Single or 4-word (4 x 32-bit) burst transfer mode
Maximum frame size allows for up to 64K bytes
S3C4510B

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