s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 264

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
MAC Station Management Data Control and Address Register
The MAC controller provides support for reading and writing station management data to the PHY. Setting
options in station management registers does not affect the controller. Some PHYs may not support the option to
suppress preambles after the first operation.
7-42
STACON
Bit Number
Registers
[15:13]
[31:16]
[4:0]
[9:5]
[10]
[11]
[12]
MDC clock rating
Reserved
PHY register address (Addr)
PHY address (PHY)
Write (Wr)
Busy bit (Busy)
Preamble suppress (PreSup)
0XA01C
Offset
Bit Name
Table 7-33. STACON Register Description
Table 7-32. STACON Register
R/W
R/W
Control the MDC period.
MD_CA[15:13]
MDC period = MD_CA[15:13]
Default MDC_CA[15:13] = 100
Not applicable.
A 5-bit address, contained in the PHY, of the register to be
read or written.
The 5-bit address of the PHY device to be read or written.
To initiate a write operation, set this bit to "1". For a read
operation, clear it to "0".
To start a read or write operation, set this bit to "1". The MAC
controller clears the Busy bit automatically when the operation
is completed.
If you set this bit, the preamble is not sent to the PHY. If it is
clear, the preamble is sent.
Station management control and address
000
001
010
111
.
.
Description
.
16
18
20
30
.
MDC period
(1/fMCLK)
(1/fMCLK)
(1/fMCLK)
(1/fMCLK)
Description
2 + 16
Reset Value
0x00008000
S3C4510B