s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 253

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
Bit Number
[31:21]
[15:8]
[16]
[17]
[18]
[19]
[20]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
BDMA Rx done every
received frame (BRxRDF)
BDMA Rx null list (BRxNL)
BDMA Rx not owner (BRxNO) If this bit is set, BDMA is not the owner of the current data
BDMA Rx maximum size over
(BRxMSO)
BDMA Rx buffer empty
(BRxEmpty)
Early notification (BRxSEarly)
Reserved
One more frame data in
BDMA receive buffer
(BRxFRF)
Number of frames in BDMA
receive buffer (BRxNFR)
BDMA Tx complete to send
control packet (BTxCCP)
BDMA Tx null list (BTxNL)
BDMA Tx not owner (BTxNO)
Reserved
BDMA Tx buffer empty
(BTxEmpty)
Reserved
Bit Name
Table 7-14. BDMA Status Register Description
This bit is set each time the BDMA receiver moves one
received data frame to memory. This bit must be cleared for
the receiving next frame interrupt generation.
If this bit is set, the BDMARXPTR has a null address. Even if
BDMA Rx is disabled, data is transferred from the MAC Rx
FIFO to the BDMA Rx buffer until the BDMA Rx buffer
overflows.
frame. The BRxSTSKO bit is set and BDMA Rx is stopped.
If this bit is set, the received frame size is larger than the value
in the Rx frame maximum size register, BDMARXLSZ.
If this bit is set, the BDMA Rx buffer is empty.
This bit is set when the BDMA receiver has received the
length/Ether-type field of the current frame.
Not applicable.
This bit is set whenever an additional data frame is received in
the BDMA receive buffer.
This value indicates the total number of data frames currently
in the BDMA receive buffer.
Bit [16] is set each time the MAC sends a complete control
packet.
If this bit is set, the BDMATXPTR value is a null address. In
this case, BDMA Tx is disabled but data continues to be
transferred from the BDMA Tx buffer to the MAC Tx FIFO until
the BDMA Tx buffer underflows. This bit is read only.
If you set BDMA Tx reset bit by software, this bit is cleared
automatically. To resume data transfer, you must then set the
new frame descriptor pointer and enable BDMA Tx.
If [18] is set, BDMA is not owner of the current frame. In this
case, the BSTSKO bit is set and BDMA Tx is stopped.
Not applicable.
If this bit is set, the BDMA Tx buffer is empty.
Not applicable.
Description
ETHERNET CONTROLLER
7-31