s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 320

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

HDLC CONTROLLERS
8-34
31
30 29 28 27 26 25
[18] Tx single flag (TxSFLAG)
0 = Double flag mode (a closing & opening flags are used to separate frames)
1 = Single flag mode (only one flags are used to separate frames)
[19] Tx loop-back mode (TxLOOP)
0 = Normal operation.
1= The tramsmit data output is internally connected to the receiver data input for self
[20] Rx echo mode (RxECHO)
0 = Disable Tx auto-echo mode.
1 = Enable Rx DMA Tx block is reset.
[21] Tx abort extension (TxABTEXT)
0 = At least consecutive eigth 1s are transferred.
1 = At least 16 consecutive 1s are transferred.
[22] Tx abort (TxABT)
0 = Normal
1 = Enable (at least eight consecutive 1s are transmitted.)
[23] Tx preamble (TxPRMB)
0 = Transmit a mark idle is time fill bit pattern.
1 = Transmit the content of HPRMB
[24] Tx data terminal ready (TxDTR)
0 = nDTR goes high level.
1 = nDTR goes low level.
[25] Rx frame discontinue (TxDISCON)
0 = Normal
1 = Ignore the currently received frame
[26] Tx No CRC (TxNOCRC)
0 = Disable
1 = CRC is not appended by hardware.
[27] Rx No CRC (RxNOCR)
0 = Disable
1 = Receiver does not check CRC by hardware.
[28] Auto enable (AutoEN)
0 = Normal operation. The nCTS and nDCD become high, the transmitter sends mark
1 = The nDCD and nCTS become high, RxFIFO, Rx block, TxFIFO, and Tx block are
[31:29] Reserved
A
E
N
u
o
t
testing.
(CRC is treated as data in any case)
cleared. The transmitter sends mark idle, and the receiver does not operate.
idle and receiver receives data.
R
N
O
C
R
C
x
O
N
C
R
C
T
x
Figure 8-15. HDLC Control Register (HCON) (Continued)
O
R
D
S
C
N
x
I
24
D
R
T
x
T
23 22
M
R
B
T
x
P
T
A
B
T
x
21
A
B
T
T
E
X
T
x
20 19
O
R
E
C
H
x
O
O
T
x
L
P
18 17 16
A
G
T
S
F
L
x
G
A
T
x
F
L
M
D
R
A
D
E
C
x
15 14
D
R
S
S
K
x
T
D
K
T
S
T
S
x
13 12 11
W
R
A
x
W
R
D
x
4
10 9
W
D
T
x
4
G
B
R
E
N
D
N
P
L
L
E
8 7 6
D
R
E
N
x
D
E
N
T
x
R
E
N
5
x
N
4
T
x
E
D
R
R
S
3
x
D
R
S
2
T
x
R
R
S
1
x
R
S
0
T
x
S3C4510B