s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 266
s3c4510b
Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C4510B.pdf
(422 pages)
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ETHERNET CONTROLLER
MAC Missed Error Count Register
The value in the missed error count register, EMISSCNT, indicates the number of packets that were discarded
due to various type of errors. Together with status information on packets transmitted and received, the missed
error count register and the two pause count registers provide the information required for station management.
Reading the missed error counter register clears the register. It is then the responsibility of software to maintain a
global count with more bits of precision.
The counter rolls over from 0x7FFF to 0x8000 and sets the corresponding bit in the MAC control register. It also
generates an interrupt if the corresponding interrupt enable bit is set. If station management software wants more
frequent interrupts, you can set the missed error count register to a value closer to the rollover value of 0x7FFF.
For example, setting a register to 0x7F00 would generate an interrupt when the count value reaches 256
occurrences.
7-44
EMISSCNT
Bit Number
Registers
[31:16]
[15:0]
Alignment error count
(AlignErrCnt)
CRC error count (CRCErrCnt)
Missed error count
(MissErrCnt)
Reserved
0XA03C
Offset
Bit Name
Table 7-37. Missed Error Count Register Description
R(Clr)/W
Table 7-36. EMISSCNT Register
R/W
The number of packets received with alignment errors. This
software counter increments at the end of a packet reception if
the Rx_Stat value indicates an alignment error.
The number of packets received with a CRC error. This
software counter increments if the Rx_Stat value indicates a
CRC error. If the Rx_Stat value indicates another type of error,
such as an alignment error, this counter is not incremented.
The number of valid packets rejected by the MAC unit
because of MAC receive FIFO overflows, parity errors, or
because the Rx_En bit was cleared. This count does not
include the number of packets rejected by the CAM.
Not applicable.
Missed error count
Description
Description
Reset Value
0x00000000
S3C4510B
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