s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 254

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
7-32
31
[0] BDMA Rx done evert received frame (BRxRDF)
0 = Reset frame data receive state.
1 = Receipt of the data frame is complete.
[1] BDMA Rx Null list (BRxNL)
0 = Reset state of new frame descriptor (BDMARXPTR) is set.
1 = Current frame descriptor address is Null (0x00000000).
[2] BDMA Rx not owner (BRxNO)
0 = BDMA is owner of the current frame.
1 = The owner of the current frame is not BDMA (CPU). In this case, BDMA Rx is
stopped and the BSTSKO bit is set.
[3] BDMA Rx maximum size over (BRxMSO)
0 = Reset state or next frame arrived at BDMA Rx buffer.
1 = Received frame exceeds the maximum frame size.
[4] BDMA Rx buffer empty (BRxEmpty)
0 = Not empty.
1 = BDMA Rx buffer empty.
[5] Early notify (BRxSEarly)
0 = Normal operation.
1 = Lengthe of current frame can be accessed by reading the BDMA receive maximum
frame size register, BDMARXLSZ [31:16].
[7] One more frame data in BDMA receive buffer (BRxFRF)
0 = Only one frame data in BDMA receive buffer.
1 = One more frame data was in the BDMA receive buffer.
[15:8] Number of frame data in BDMA receive buffer (BRxNFR)
[16] BDMA Tx complete to send control packet (BTxCCP)
0 = Clear but by writing a 1 to this bit or by resetting BDMA Tx.
1 = MAC complete to send the control packet.
[17] BDMA Tx Null list (BTxNL)
0 = Reset stste of new frame descriptor (BDMATXPTR) is set.
1 = Current frame descriptor address is Null (0x00000000).
[18] BDMA Tx not owner (BTxNO)
0 = BDMA is owner of the current frame.
1 = The owner of the current frame is not BDMA (CPU). In this case, BDMA Tx is
[19] Reserved
[20] BDMA Tx buffer empty (BTxEmpty)
0 = Not empty
1 = BDMA Tx buffer empty.
[31:21] Reserved
NOTE:
Reserved
stopped if the BTxSTSKO bit is set to one.
Bit 0, 1, 2, 3, 4, 16, 17, 18 and 20 should be cleared for interrupt generation
for the next frame. The method is write 1 to the corresponding bit location.
21 20 19 18 17
B
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Figure 7-14. BDMA Status Register
X
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16 15
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4
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3
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0
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S3C4510B