s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 344

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

DMA CONTROLLER
S3C4510B
GDMA FUNCTION DESCRIPTION
The following sections provide a functional description of the GDMA controller operations.
GDMA TRANSFERS
The GDMA transfers data directly between a requester and a target. The requester and target are memory,UART
or external devices. An external device requests GDMA service by activating nXDREQ signal. A channel is
programmed by writing to registers which contain requester address, target address, the amount of data, and
other control contents. UART, external I/O, or Software(memory) can request GDMA service. UART is internally
connected to the GDMA.
STARTING/ENDING GDMA TRANSFERS
GDMA starts to transfer data after the GDMA receives service request from nXDREQ signal, UART, or Software.
When the entire buffer of data has been transferred, the GDMA becomes idle. If you want to preform another
buffer transfer, the GDMA must be reprogrammed. Although the same buffer transfer wii be preformed again, the
GDMA must be reprogrammed.
DATA TRANSFER MODES
Single Mode
A GDMA request (nXDREQ or an internal request) causes one byte, one half-word, or one word to be transmitted
if 4-data burst mode is disable state, or four times of transfer width if 4-data burst mode is enable state. Single
mode requires a GDMA request for each data transfer. The nXDREQ signal can be de-asserted after checking
that nXDACK has been asserted.
nXDREQ
nXDACK
RD/WR Cycle
Figure 9-5. External DMA Requests (Single Mode)
9-8