s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 275

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
The back_off State Machine
The back_off state machine implements the back-off and retry algorithm of the 802.3 CSMA/CD. When a
collision is detected, the main transmit state machine starts the back_off state machine s counters and waits for
the back-off time (including zero) to elapse. This time is a multiple of 512 bit times that elapse before the packet
that caused the collision is re-transmitted.
Each time there is a collision (for one single packet), the back_off state machine increments an internal retry
attempt countner. A 11-bit pseudo random number generator outputs a random number by selecting a subset of
the value of the generator at any time. The subset is incremented by one bit for each subsequent attempt. This
implementation is represented by the following equation:
For example, after the first collision, "n" is 1 and "r" is a random number between 0 and 1. The pseudo random
generator in this case is one-bit wide and gives a random number of either 0 or 1. After the second attempt, "r" is
a random number between 0 and 3. Therefore, the state machine looks at the two least-significant bits of the
random generator (n = 2), which gives a value between 0 and 3.
The Main Transmit State Machine
The main transmit state machine implements the remaining MAC layer protocols. If there is data to be
transferred, if the inter-frame gap is valid, and if the MII is ready (that is, if there are no collisions and no CRS in
full-duplex mode), the transmit block then transmits the preamble followed by the SFD.
After the SFD and preamble are transmitted, the block transmits 64 bytes of the data, regardless of the packet
length, unless short transmission is enabled. This means that if the packet is less than 64 bytes, it will pad the
LLC data field with zeros. It will also appends the CRC to the end of the packet, if CRC generation is enabled.
If there is any collision during this first 72 bytes (8 bytes of preamble and SFD, and 64 bytes of the frame), the
main transmit state machine stops the transmission and transmits a jam pattern (32 bits of 1 s). It then
increments the collision attempt counter, returns control to the back_off state machine, and re-transmits the
packet when the back-off time has elapsed and the gap time is valid.
If there are no collisions, the transmit block transmits the rest of the packet. At this time (that is, after the first 60
bytes have been transmitted without collisions), the main transmit state machine lets the BDMA engine overwrite
the packet. After it transmits the first 64 bytes, the transmit block transmits the rest of the packet, appending the
CRC to the end. parity errors, FIFO errors, or more than 16 collisions will cause the transmit state machine to
abort the packet (no retry) and queue up the next packet.
In case of any transmission errors, the transmit block sets the appropriate error bit in the transmit status register.
It may also generate an interrupt, depending on the enable bit settings in the transmit control register.
0 =< random integer(r) < 2
K = min (n, backoff limit (= 10))
where "r" is the number of slot times the MAC must wait in case of a collision, and "n" is the number of retry
attempts.
K
ETHERNET CONTROLLER
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