s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 242

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
7-20
[19:16] Transmit collision count (TxCollCnt)
Count of collisions during transmission of a single packet. After 16 collisions, TxColl
is zero, and ExColl is set.
[20] Excessive collision (ExColl)
16 collisions occured in the same packet.
[21] Transmit deferred (TxDefer)
[22] Paused
[23] Interrupt on transmit (IntTx)
Set if transmission of packet caused an interrupt condition. This includes the enable
completion (EnComp), MACTXCON [14], if enabled.
[24] Underrun (Under)
MAC transmit FIFO becomes empty during transmission.
[25] Deferral (Defer)
MAC defers for max_deferral 0.32768ms for 100Mbit/s or 3.27680ms for 10Mbit/s.
[26] No carrier (NCarr)
Carrier sense is not detected during the entire transmission of a packet
(from the SFD to the CRC).
[27] SQE error (SQErr)
After transmit frame, set if the fake collision (COL) signal did not come from the PHY
for 1.6 s.
[28] Late collision (LateColl)
A collision occurred after 512 bit times (64 byte times)
[29] Transmit parity error (TxPar)
MAC transmit FIFO detected a parity error.
[30] Completion (Comp)
MAC complete a transmit or discard of one packet.
[31] Transmission halted (TxHalted)
Transmission halted by clearing RxEn or setting the Haltlmm in the MAC control
register. Or, an interrupt was generated by an error condition (not completion).
Tx Status
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Figure 7-9. Tx Descriptor Status Bits
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TxCollCnt
16
S3C4510B