s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 295

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
DIGITAL PHASE-LOCKED LOOP (DPLL)
The HDLC module contains a digital phase-locked loop (DPLL) function to recover clock information from a data
stream with NRZI or FM encoding. The DPLL is driven by a clock that is normally 32 (NRZI) or 16 (FM) times the
data rate. The DPLL uses this clock, along with the data stream, to construct the clock.
This clock may then be used as the receive clock, the transmit clock, or both.
Figure 8-3 shows a block diagram of the digital phase-locked loop. It consists of a 5-bit counter, an edge detector
and a pair of output decoders.
CLOCK USAGE METHOD
DPLLOUTT
BRGOUT1
BRGOUT2
NOTE:
BRGOUT1
BRGOUT2
MCLK2
RxC
RxC
TxC
MCLK
RxD
RxC
TxC
BRGCLK = HMODE [19]
DPLLCLK = HMODE [18:16]
TxCLK = HMODE [22:20]
RxCLK = HMODE [26:24]
HMODE[18:16]
BRGCLK
TxCLK
Detector
Edge
Transmit
Clock
Baud Rate
Generator
Figure 8-4. Clock Usage Method Diagram
Transmitter
Count Modifier
5-bit Counter
Figure 8-3. DPLL Block Diagram
BRGOUT1
BRGOUT2
Transmit
Data
DPLLOUTT
BRGOUT1
BRGOUT2
BRGOUT1
BRGOUT2
MCLK
RxC
RxC
TxC
TxC
Decoder
Decoder
DPLLCLK
RxCLK
Receive Clock
Transmit clock
Receive
Clock
DPLL
Receiver
HDLC CONTROLLERS
dplloutR
dplloutT
DPLLOUTT
DPLLORTR
Receive
Data
8-9