s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 203

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
REFEXTCON
31
Figure 4-37. DRAM Refresh and External I/O Control Register (REFEXTCON)
Refresh Count Value
[9:0] External I/O bank 0 base pointer (base address)
This value is the start address of I/O external I/O bank 0. Start address is defined as
external I/O bank 0 base pointer << 16. The end address of external I/O bank 0 is defined
as external I/O bank 0 base pointer >> 16 + 16 Kbytes - 1.
NOTE:
begins at the start address of external I/O bank 0. The size of each external I/O bank
is fixed at 16Kbytes. The start and end addresses of the other three external I/O banks
can be derived from the external I/O bank 0 base pointer value.
[15] Validity of spedial register field (VSF)
0 = Not accessible to memory bank
1 = Accessible to memory bank
[16] Refresh enable (REN)
0 = Disable DRAM refresh
1 = Enable DRAM refresh
[19:17] CAS hold time (tCHR)
000 = 1 cycle
010 = 3 cycles
100 = 5 cycles
110 = Not used
[20] CAS setup time (tCSR)
0 = 1 cycle
1 = 2 cycles
[31:21] Refresh count value (duration)
The refresh period is calculate as (2
NOTES:
1.
2.
In EDO/normal DRAM mode, CAS hold time can be
In SDRAM mode, this bit field is reserved.
programmed upto 5 cycles. But in SDRAM mode, this
bit fields function are defined as ROW cycle time (tRC)
and can be programmed upto 6 cycles.
ROW cycle time (tRC)
All external I/O banks are located in the continuous address space which
21
20
C
R
S
t
19
(Note 2)
tCHR
(Note 1)
001 = 2 cycles
011 = 4 cycles
101 = Not used (6 cycles)
111 = Not used
17 16 15 14 13 12 11
11
- value + 1)/fMCK
R
E
N
V
S
F
0 0 0 0 0
10 9
External I/O Bank 0
Base Pointer
SYSTEM MANAGER
4-61
0