s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 326

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

HDLC CONTROLLERS
8-40
31
M
D
P
L
L
T
30 29 28 27 26 25
O
M
D
P
L
L
O
D
T
N
[16] Rx abort (RxABT)
0= Normal operation
1 = Seven or more consecutive 1s have been received, in-frame condition.
[17] Rx CRC error (RxCRCE)
0 = Normal operation
1 = A frame Rx operation is completed with a CRC error.
[18] Rx non-octet align (RxNO)
0 = Received frame is octet.
1 = Received frame is not octet.
[19] Rx overrun (RxOV)
0 = Normal operation
1 = Received data is transferred into the RxFIFO when it is full.
[20] Rx memory overflow (RxMOV)
0 = Normal operation
1 = Indicates memory overflow when Rx buffer descriptor next pointer has null address.
[21] Reserved
[22] DMA Tx abort (DTxABT)
0 = Normal operation
1 = Abort signal is sended and DMA Tx enable bit is cleared.
[23] Rx internal error (RxIERR)
0 = Normal operation
1 = Received frame is not stable due to receive clock is unstable.
[24] DMA Rx frame done every received frame (DRxFD)
0 = Normal operation
1 = DMA Rx operation has successfully transferred a frame from RxFIFO to buffer memory.
[25] DMA Rx null list (DRxNL)
0 = Normal operation
1 = DMA Rx buffer descriptor pointer has a null address.
[26] DMA Rx not owner (DRxNO)
0 = DMA has the ownership.
1 = CPU has the ownership.
[27] DMA Tx frame done (DTxFD)
0 = Normal operation
1 = DMA Tx operation has successfully transferred a frame from memory to TxFIFO.
[28] DMA Tx null list (DTxNL)
0 = Normal operation
1 = DMA Tx buffer descriptor pointer has a null address.
[29] DMA Tx not owner (DTxNO)
0 = DMA has the ownership.
1 = CPU has the ownership.
[30] DPLL one clock missing (DPLLOM)
0 = Normal operation
1 = Set in FM/Machester mode when DPLL does not detect an edge on the first entry.
[31] DPLL two clock missing (DPLLTM)
0 = Normal operation
1 = DPLL was not detected on two consecutive edges and search mode was entered.
x
D
N
T
x
L
D
D
T
F
x
O
D
R
N
x
D
R
N
L
x
24
D
R
D
x
F
Figure 8-17. HDLC Status Register (Continued)
23 22
R
R
R
x
E
I
D
T
A
B
T
x
21
20 19
M
O
R
V
x
R
O
x
V
18 17 16
R
N
O
x
R
C
R
C
x
E
R
A
B
T
x
15 14
R
D
E
x
L
I
R
F
V
x
13 12 11
R
D
C
D
x
S
R
D
C
D
x
R
D
x
F
10 9
R
A
x
F
U
T
8 7 6
x
S
C
S
T
x
T
C
S
T
x
T
A
5
T
x
F
C
4
T
x
F
3
2
R
R
B
x
1
0
S3C4510B