s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 213

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
I
Basic Operation
The I
ICs connected to the bus. Each IC is recognized by a unique address and can operate as either a transmitter or
receiver, depending on the function of the specific ICs.
The I
be connected to it. data transfers proceed as follows:
Case 1: A master IC wants to send data to another IC (slave):
1. Master addresses slave
2. Master sends data to the slave (master is transmitter, slave is receiver)
3. Master terminates the data transfer
Case 2: A master IC wants to receive information from another IC (slave):
1. Master addresses slave
2. Master receives data from the slave (master is receiver, slave is transmitter)
3. Master terminates the data transfer
Even in case 2, the master IC must generate the timing signals and terminate the data transfer.
If two or more masters try to put information simultaneously onto the bus, the first master to issue a "1" when the
other issues a "0" will lose the bus arbitration. The clock signals used for arbitration are a synchronized
combination of the clocks generated by the bus masters using the wired-AND connection to the SCL line.
The master IC is always responsible for generating the clock signals on the I
master can only be altered by 1) a slow slave IC which "stretches" the signal by temporarily holding the clock line
Low, or 2) by another master IC during arbitration.
General Characteristics
Both SDA and SCL are bi-directional lines which are connected to a positive supply voltage through a pull-up
resistor.
When the I
connected to the bus have an open-drain or open-collector to perform the wired-AND function. Data on the I
bus can be transferred at a rate up to 100 Kbits/s. The number of interfaces that can be connected to the bus is
solely dependent on the limiting bus capacitance of 400 pF.
Bit Transfers
Due to the variety of different ICs (CMOS, NMOS, and I2L, for example) which can be connected to the I
the levels of logic zero (low) and logic one (high) are not fixed and depend on the associated level of V
clock pulse is generated for each data bit that is transferred.
2
C-BUS CONCEPTS
2
2
C-bus has two wires, a serial data line (SDL) and a serial clock line (SCL), to carry information between the
C-bus is a multi-master bus. This means that more than one IC which is capable of controlling the bus can
2
C-bus is free, the SDA and SCL lines are both high level. The output stages of I
2
C-bus. Bus clock signals from a
I
2
2
C BUS CONTROLLER
C interfaces
DD
2
. One
C-bus,
2
C-
6-3