s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 260

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
MAC Transmit Status Register
A transmission status flag is set in the transmit status register, MACTXSTAT, whenever the corresponding event
occurs. In addition, an interrupt is generated if the corresponding enable bit in the transmit control register is set.
A MAC transmit FIFO parity error sets TxPar, and also clears TxEn, if the interrupt is enabled.
You can read and mask the five low-order bits as a single collision count. That is, when ExColl is "1", TxColl is
"0". If TxColl is not "0", then ExColl is "0".
7-38
MACTXSTAT
Bit Number
Registers
[31:16]
[3:0]
[10]
[11]
[12]
[13]
[14]
[15]
[4]
[5]
[6]
[7]
[8]
[9]
Transmit collision count
(TxColl)
Excessive collision (ExColl)
Transmit deferred (TxDeferred) This bit is set if transmission of a packet was deferred
Paused (Paused)
Interrupt on transmit (IntTx)
Underrun (Under)
Deferral (Defer)
No carrier (NCarr)
Signal quality error (SQE)
Late collision (LateColl)
Transmit parity error (TxPar)
Completion (Comp)
Transmission halted (TxHalted) Transmission was halted by clearing the TxEn bit or the halt
Reserved
0XA00C
Offset
Table 7-25. MAC Transmit Status Register Description
Bit Name
Table 7-24. MACTXSTAT Register
R/W
R/W
Transmit status
This 4-bit value is the count of collisions that occurred while
successfully transmitting the packet.
This bit is set if 16 collisions occur while transmitting the
same packet. In this case, packet transmission is aborted.
because of a delay during transmission.
This bit is set if transmission of a packet was delayed due to
a Pause being received.
This bit is set if transmission of a packet causes an interrupt
condition.
This bit is set if the MAC transmit FIFO becomes empty
during a packet transmission.
This bit is set if the MAC defers a transfer because of
MAX_DEFERRAL at 0.32768 ms for 100 Mb/s or 3.2768 ms
for 10Mb/s.
This bit is set if no carrier sense is detected during the
transmission a packet.
According to the IEEE802.3 rule, the SQE signal reports the
status of the PMA (MAU or transceiver) operation to the MAC
layer. After transmission is complete and 1.6 s has elapsed,
a collision detection signal is issued for 1.5 s to the MAC
layer. This signal is called the SQE test signal. The MAC sets
the SQE bit in the MACTXSTAT register if this signal is not
reported within the IFG time of 6.4 s.
This bit is set if a collision occurs after 512 bit times (or 64
byte times).
This bit is set if a collision occurs after 512 bit times (or 64
byte times).
This bit is set when the MAC transmits, or discards, one
packet.
immediate (HaltImm) bit.
Not applicable.
Description
Description
Reset Value
0x00000000
S3C4510B