s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 39

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
IRQ
The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a
lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by
setting the I bit in the CPSR, though this can only be done from a privileged (non-User) mode.
Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler should return from
the interrupt by executing
Abort
An abort indicates that the current memory access cannot be completed. It can be signalled by the external
ABORT input. ARM7TDMI checks for the abort exception during memory access cycles.
There are two types of abort:
—
— Data abort: occurs during a data access.
If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until
the instruction reaches the head of the pipeline. If the instruction is not executed - for example because a branch
occurs while it is in the pipeline - the abort does not take place.
If a data abort occurs, the action taken depends on the instruction type:
—
—
—
The abort mechanism allows the implementation of a demand paged virtual memory system. In such a system
the processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the
Memory Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort,
make the requested data available, and retry the aborted instruction. The application program needs no
knowledge of the amount of memory available to it, nor is its state in any way affected by the abort.
After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or
Thumb):
This restores both the PC and the CPSR, and retries the aborted instruction.
Prefetch abort: occurs during an instruction prefetch.
Single data transfer instructions (LDR, STR) write back modified base registers: the Abort handler must be
aware of this.
The swap instruction (SWP) is aborted as though it had not been executed.
Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the
instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is
prevented. All register overwriting is prevented after an abort is indicated, which means in particular that R15
(always the last register to be transferred) is preserved in an aborted LDM instruction.
SUBS
SUBS
SUBS
PC,R14_irq,#4
PC,R14_abt,#4
PC,R14_abt,#8
; for a prefetch abort, or
; for a data abort
PROGRAMMER'S MODEL
2-13