s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 272

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
S3C4510B
TRANSMITTING A FRAME
To transmit a frame, the transmit enable bit in the transmit control register must be set and the transmit halt
request bit must be zero. In addition, the halt immediate and halt request bits in the MAC control register must be
"0". These conditions are normally set after any BDMA controller initialization has occurred. The system then
uses the Tx_wr# and Tx_EOF signals to transfer bytes to the transmit data buffer.
The transmit state machine starts transmitting the data in the FIFO, and will retain the first 64 bytes until after
this station has acquired the net. At that time, the transmit block requests more data and transmits it until the
system asserts the Tx_EOF input, signaling the end of data to be transmitted. The transmit block appends the
calculated CRC to the end of the packet, and transmission ends. It then sets the transmit status register bit 0,
signaling a successful transmission. This action may causes an interrupt, if enabled.
A frame transmit operation can be subdivided into two operations, 1) a MII interface operation, and 2) a BDMA/
MAC interface operation.
BDI TRANSMIT OPERATION
The BDI transmit operation is a simple FIFO mechanism. The BDMA engine stores data to be transmitted, and
the transmit state machine empties it when the MAC successfully acquires the net.
Note that the two time domains intersect at the FIFO controller. The writing and reading of data is asynchronous
and on different clocks. Reading is driven by either a 25-MHz or a 2.5-MHz transmit clock. Writing is driven by
the synchronous Sys_clk, which is asynchronous to Tx_clk.
After a reset, the transmit FIFO is empty. The transmit block asserts the Tx_rdy signal, and transmission is
disabled. To enable transmission, the system must set the transmit enable bit in the transmit control register. In
addition, eight bytes of data must be present in the transmit FIFO. The BDMA engine can start stuffing data into
the FIFO, and then enable the transmit bit. (Or it can enable the transmit bit first and then start stuffing data into
the FIFO.) The transmit operation can only start if both of these conditions are met.
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