s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 230

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
S3C4510B
Transmit FIFO and Read/Write Controllers
The transmit FIFO has an 80-byte depth. An extra bit is associated with each data byte for parity checking. This
80-byte by 9-bit size allows the first 64 bytes of a data packet to be stored and retransmitted, without further
system involvement, in case of a collision. If no collision occurs and transmission is underway, the additional 16
bytes handle system latency and avoid FIFO under-run.
When the system interface has set the transmit enable bit in the appropriate control register, the transmit state
machine requests data from the BDI. The system controller then fetches data from the system memory.
The FIFO controller stores data in the transmit FIFO until the threshold for transmit data is satisfied. The FIFO
controller passes a handshaking signal to the transmit state machine, indicating that sufficient data is in the FIFO
to start the transmit operation. If the FIFO is not full, the FIFO controller issues a request to the BDI for more
data. The transmit state machine continues transmitting data until it detects the end-of-frame signal, which
signals the last byte. It then appends the calculated CRC to the end of the data (unless the CRC truncate bit in
the transmit control register is set). The packet transmit bit in the status register is set, generating an interrupt if it
is enabled.
The FIFO counters in this block (the Write counter) and the transmit FIFO counter of the transmit state machine
(the Read counter) co-ordinate their functions based on each other's count value, although they do have different
clock sources.
The FIFO controller stores parity bits with the data in the FIFO. It checks for parity and can halt transmission
after reading the data out of the FIFO and sending it for the CRC calculation. If a parity error occurs, the FIFO
controller sets an error status bit, generating an interrupt if it is enabled.
Preamble and Jam Generator
As soon as the transmit enable bit in the control register is set and there are eight bytes of data in the FIFO, the
transmit state machine starts the transmission by asserting the Tx_en signal and transmitting the preamble and
the start frame delimiter (SFD). In case there is a collision, it transmits a 32-bit string of "1s" after the preamble
as a jam pattern.
PAD Generator
If a short data packet is transmitted, the MAC will normally generate pad bytes to extend the packet to a
minimum of 64 bytes. The pad bytes consist entirely of "0" bits. A control bit is also used to suppress the
generation of pad bytes.
Parallel CRC Generator
The CRC generation of the outgoing data starts from the destination address and continues through the data
field. You can suppress CRC generation by setting the appropriate bit in the transmit control register. This is
useful in testing, for example, to force the transmission of a bad CRC in order to test error detection in the
receiver. It can also be useful in certain bridge or switch applications, where end-to-end CRC checking is desired.
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