SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 1061

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

1: The Master Interface Arbiter is locked by the channel x for a buffer transfer.
• AHB_PROT
AHB_PROT field provides additional information about a bus access and is primarily used to implement some level of
protection.
• FIFOCFG
6430E–ATARM–29-Aug-11
AHB_PROT[2]
HPROT[3]
FIFOCFG
00
01
10
When there is enough space/data available to perform a single AHB access, then the request is serviced.
AHB_PROT[1]
HPROT[2]
The largest defined length AHB burst is performed on the destination AHB interface.
When half FIFO size is available/filled, a source/destination request is serviced.
AHB_PROT[0]
HPROT[1]
FIFO request
HPROT[0]
1
SAM3U Series
1: Privileged Access
0: Not Bufferable
0: Not cacheable
0: User Access
1: Cacheable
1: Bufferable
Data access
Description
1061