SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 1166

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

1166
Doc.
Rev.
6430C
SAM3U Series
RTC:
Section 18.3.2
Section 18.5 ”Real Time Clock (RTC) User
TIMEVSEL, CALEVSEL bitfield descriptions reorganized.
SSC:
Redundant letter C removed from title.
SUPC:
Section 19.4 ”Supply Controller (SUPC) User
FWUPDBC, WUPDBC bitfield descriptions reorganized.
Backup supply is VDDBU
TC:
Figure 36-2 ”Clock Chaining
updated bitfields: TC0XC0S, TC1XC1S, TC2XC2S, TCCLKS, BURST, ETRGEDG, LDRA, LDRB, TCCLKS,
BURST, EEVTEDG, EEVT, WAVSEL, ACPA, ACPC, AEEVT, ASWTRG, BCPB, BCPC, BEEVT, BSWTRG
UDHP:
Figure 39-4 ”Logical Address Space for DPR
Figure 39-1 ”Block
Figure 39.4 ”Product
Figure 39-6 ”Register
USART:
Section 35.6.7 ”Modem
Section 35.6 ”Functional
Section 35.6.8.2 ”Baud Rate”
SPI Master Mode: ...”the value programmed in CD must be superior or equal to 6.”
SPI Slave Mode:...”the external clock (SCK) frequency must be at least 6 times lower than the system clock.”
Section 35.6.1 ”Baud Rate
USART mode, or 6 in SPI mode.”
Section 35.6.1.3 ”Baud Rate in Synchronous Mode or SPI
MCK/3 in USART mode, or MCK/6 in SPI mode.”
Comments (Continued)
”Interrupt”, updated.
Diagram”, 1 PMC to UTMI signal line. Notes removed.
Dependencies”, added to datasheet.
Mapping”, DMA offset updated to 0x300 + channel *...
Mode”, is available.
Description”, ...SCK up to MCK/6
Generator”,”...signal provided on SCK must be at least 3 times lower than MCK in
Selection”, channel 1 updated.
Interface”, the reset for RTC_CALR is 0x01210720.
Access”, EP0 has but 1 bank
Interface”, offset updated for GPBR: 0x90-0xDC.
Mode”, ...”limits the SCK maximum frequency to
6430E–ATARM–29-Aug-11
Change
Request
Ref.
7071
7046/7087
6796
6949
6950
6796
6714
6687
6796
6750
6792
rfo
6822
6791
rfo→ 7097