SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 965

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 39-8. Data IN Transfer for Endpoint with One Bank
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
USB Bus
Packets
TX_PK_RDY
Flag
(UDPHS_EPTSTAx)
TX_COMPLT Flag
(UDPHS_EPTSTAx)
FIFO
Content
Token IN
Set by firmware
Prevous Data IN TX
ory address pointed by the UDPHS_DMANXTDSCx register. Once the transfer is complete, the
transfer status is updated in the UDPHS_DMASTATUSx register.
To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be
stopped. To do so, INTDIS_DMA and TX_BK_RDY may be set in the UDPHS_EPTCTLENBx
register. It is also possible for the application to wait for the completion of all transfers. In this
case the LDNXT_DSC field in the last transfer descriptor UDPHS_DMACONTROLx register
must be set to 0 and CHANN_ENB set to 1.
Then the application can chain a new transfer descriptor.
The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is trig-
gered. This can be used to stop DMA transfers in case of errors.
The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the
UDPHS_DMACONTROLx register).
Data IN 1
Data IN 1
Cleared by hardware
Set by hardware
ACK
DPR access by firmware
Microcontroller Loads Data in FIFO
Token IN
Load in progress
Interrupt Pending
NAK
Set by the firmware
Token IN
Cleared by firmware
Data is Sent on USB Bus
DPR access by hardware
Data IN 2
Payload in FIFO
Data IN 2
SAM3U Series
SAM3U Series
Cleared by hardware
Cleared by firmware
Interrupt Pending
ACK
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