SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 606

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

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SAM3U Series
SAM3U Series
nected to other peripherals are in use as well, the SPI DMAC might be delayed by another
(DMAC with a higher priority on the bus). Having DMAC buffers in slower memories like flash
memory or SDRAM compared to fast internal SRAM, may lengthen the reload time of the
SPI_TDR by the DMAC as well. This means that the SPI_TDR might not be reloaded in time to
keep the chip select line low. In this case the chip select line may toggle between data transfer
and according to some SPI Slave devices, the communication might get lost. The use of the
CSAAT bit might be needed.
When the CSAAT bit is set at 0, the NPCS does not rise in all cases between two transfers on
the same peripheral. During a transfer on a Chip Select, the flag TDRE rises as soon as the con-
tent of the SPI_TDR is transferred into the internal shifter. When this flag is detected the
SPI_TDR can be reloaded. If this reload occurs before the end of the current transfer and if the
next transfer is performed on the same chip select as the current transfer, the Chip Select is not
de-asserted between the two transfers. This might lead to difficulties for interfacing with some
serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate
interfacing with such devices, the Chip Select Register can be programmed with the CSNAAT bit
(Chip Select Not Active After Transfer) at 1. This allows to de-assert systematically the chip
select lines during a time DLYBCS. (The value of the CSNAAT bit is taken into account only if
the CSAAT bit is set at 0 for the same Chip Select).
Figure 32-10
CSNAAT bits.
shows different peripheral deselection cases and the effect of the CSAAT and
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11