SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 564
SAM3U1C
Manufacturer Part Number
SAM3U1C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U1C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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SAM3U Series
SAM3U Series
Write Protection Registers
To prevent any single software error that may corrupt SSC behavior, certain address spaces can
be write-protected by setting the WPEN bit in the
(SSC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Pro-
tect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the
write access has been attempted.
The WPVS flag is reset by writing the SSC Write Protect Mode Register (SSC_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
•
•
•
•
•
•
•
“SSC Clock Mode Register” on page 567
“SSC Receive Clock Mode Register” on page 568
“SSC Receive Frame Mode Register” on page 570
“SSC Transmit Clock Mode Register” on page 572
“SSC Transmit Frame Mode Register” on page 574
“SSC Receive Compare 0 Register” on page 580
“SSC Receive Compare 1 Register” on page 581
“SSC Write Protect Mode Register”
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
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