SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 892

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

38.6.3
892
892
SAM3U Series
SAM3U Series
PWM Comparison Units
The PWM provides
the current value of the channel 0 counter (which is the channel counter of all synchronous
channels,
erate pulses on the event lines (used to synchronize ADC, see
Lines”), to generate software interrupts and to trigger PDC transfer requests for the synchronous
channels (see
update” on page
Figure 38-13. Comparison Unit Block Diagram
The comparison x matches when it is enabled by the bit CEN in the
Register”
the comparison value defined by the field CV in
(PWM_CMPVx for the comparison x). If the counter of the channel 0 is center aligned (CALG =
1 in
is made when the counter is counting up or counting down (in left alignment mode CALG=0, this
bit is useless).
If a fault is active on the channel 0, the comparison is disabled and cannot match (see
38.6.2.5 “Fault
The user can define the periodicity of the comparison x by the fields CTR and CPR (in
PWM_CMPVx). The comparison is performed periodically once every CPR+1 periods of the
counter of the channel 0, when the value of the comparison period counter CPRCNT (in
PWM_CMPMx) reaches the value defined by CTR. CPR is the maximum value of the compari-
son period counter CPRCNT. If CPR=CTR=0, the comparison is performed at each period of the
counter of the channel 0.
The comparison x configuration can be modified while the channel 0 is enabled by using the
“PWM Comparison x Mode Update Register”
x). In the same way, the comparison x value can be modified while the channel 0 is enabled by
using the
comparison x).
“PWM Channel Mode Register”
“PWM Comparison x Value Update Register”
Section 38.6.2.6 “Synchronous
(PWM_CMPMx for the comparison x) and when the counter of the channel 0 reaches
Protection”).
CEN [PWM_CMPM]x
fault on channel 0
CV [PWM_CMPVx]
CNT [PWM_CCNT0]
CNT [PWM_CCNT0] is decrementing
CVM [PWM_CMPVx]
CALG [PWM_CMR0]
CPRCNT [PWM_CMPMx]
CTR [PWM_CMPMx]
“Method 3: Automatic write of duty-cycle values and automatic trigger of the
889).
8
independent comparison units able to compare a programmed value with
), the bit CVM (in PWM_CMPVx) defines if the comparison
Channels”). These comparisons are intended to gen-
=
=
=
(PWM_CMPMUPDx registers for the comparison
1
0
1
“PWM Comparison x Value Register”
(PWM_CMPVUPDx registers for the
Section 38.6.4 “PWM Event
“PWM Comparison x Mode
Comparison x
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
Section