SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 1169

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6430E–ATARM–29-Aug-11
Doc Rev
6430B
PMC:
Section 28.14.16 ”PMC Interrupt Mask
28.14.14 ”PMC Interrupt Disable
Section 28.13 ”Write Protection
Section 28.14.20 ”PMC Write Protect Mode Register”
Section 28.10 ”Clock Failure
Section 28.11 ”Programming
removed code example, bitfield names updated.
PWM:
Table 38-4, “Fault
RSTC:
Section 16.2 ”Block
Section 16.3.1 ”Reset Controller
Comments (Continued)
CORTEX-M3:
Table 13-31, “Priority
Section 13.19.7.1
Section 13.5.2.2 ”Non Maskable Interrupt (NMI)”
Section 13.6.2 ”Fault escalation and hard
Section 13.3.5 ”Data types”
Table 13-11,
Table 13-29, “CMSIS functions for NVIC
on page
Table 13-4, “Memory access
Big Endien not used in this product.
Debug and Test:
Section 14.1
Table 14-1, “Debug and Test Signal
FFPI:
Section 22.2.5.4 ”Flash Lock
HSMCI:
Section 37.12 ”Write Protection
Section 37.13.19 ”HSMCI Write Protect Status
MATRIX:
Table 24-1, “Register
PDC:
Section 26. ”Peripheral DMA Controller (PDC)”
PIO:
Section 30.5.1 ”Write Protection
30.6.43 ”PIO Write Protect Status Register”
Section 16.3.4.2 ”Backup
“backup_nreset” replaces “core_backup_reset”.
SMC:
Table 25-4, “External Memory
Section 13.20.6 ”Application Interrupt and Reset Control
53, “...copyright ARM Ltd., 2008 - 2009.” precise years given.
”Overview”, SWJ-DP...also embeds a serial trace.
“Faults,”updated footnote 1
”IP27”, title changed to IP27, value in bitfields 0 to 7 changed to IP28.
Inputs”, “PWM Fault Input Number” column, typos fixed
Diagram”, “backup_nreset” replaces “core_backup_reset”.
grouping,”updated.
Mapping”, added offsets for Write Protection Registers
Reset”, “The vddcore_nreset signal is asserted by the SUPC...” and
Condition tags sorted out.
Detector”, added sentence on Fast RC
behavior,”last row assinged to Reserved in Memory Map.
Commands”, last sentence removed from 2nd paragraph (ref to EA command).
Sequence”, added step 1 and reordered subsequent numbering sequence.
Mapping”, restored rows for chip selects 0, 1, 2 to the table.
Registers”,
Registers”,
Registers”,
Overview”, RSTC_MR...”is powered with VDDBU...”
Register”, 0 and 1read or write values described.
List”, reorganized.
Register”,
control,”Description in 4th row updated.
faults”, last sentence updated with NMI function.
Section 37.13.18 ”HSMCI Write Protect Mode Register”
Section 28.14.20 ”PMC Write Protect Mode Register”
Section 30.6.42 ”PIO Write Protect Mode Register”
added with links to protected registers.
Register”,added.
Section replaced.
added to datasheet.
Section 28.14.13 ”PMC Interrupt Enable
added with links to protected registers.
Register”read/write values to VECTKEY changed
Register”,
SAM3U Series
and
and
and
Section
Section
Change
Request
Ref.
6394:
6436
6483
rfo
rfo
6677
6432
6431
6468
6430
6311/rfo
6432
6469
6591
rfo
6397
rfo
6397
1169