SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 698

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

35.7.1.2
Figure 35-4. Fractional Baud Rate Generator
35.7.1.3
698
698
SCK
Reserved
MCK/DIV
SAM3U Series
SAM3U Series
MCK
Fractional Baud Rate in Asynchronous Mode
Baud Rate in Synchronous Mode or SPI Mode
USCLKS
0
1
2
3
The Baud Rate generator previously defined is subject to the following limitation: the output fre-
quency changes by only integer multiples of the reference frequency. An approach to this
problem is to integrate a fractional N clock generator that has a high resolution. The generator
architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
This fractional part is programmed with the FP field in the Baud Rate Generator Register
(US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the
clock divider. This feature is only available when using USART normal mode. The fractional
Baud Rate is calculated using the following formula:
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 3 times lower than the
Baudrate
BaudRate
16-bit Counter
CD
=
---------------------------------------------------------------- -
⎛
⎝
8 2 Over
Modulus
=
Control
(
FP
SelectedClock
------------------------------------- -
SelectedClock
–
CD
) CD
⎛
⎝
glitch-free
USCLKS = 3
+
logic
FP
------ -
FP
8
⎞
⎠
⎞
⎠
SYNC
0
CD
>1
1
0
1
0
OVER
Sampling
Divider
FIDI
0
1
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
SYNC
SCK
Baud Rate
Sampling
Clock
Clock