SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 913

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

38.7.9
Name:
Address:
Access:
This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in
page
• SYNCx: Synchronous Channel x
0 = Channel x is not a synchronous channel.
1 = Channel x is a synchronous channel.
• UPDM: Synchronous Channels Update Mode
Notes:
• PTRM: PDC Transfer Request Mode
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
Value
0
1
2
3
UPDM
936.
31
23
15
–
–
7
–
0
1
2
1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in
2. The update occurs when the Update Period is elapsed.
PWM Sync Channels Mode Register
Control Register”
PWM_SCM
0x4008C020
Read-write
MODE0
MODE1
MODE2
Name
–
PTRCS
PTRM
30
22
14
–
–
6
–
0
1
x
x
is set.
Manual write of double buffer registers and manual update of synchronous channels
Manual write of double buffer registers and automatic update of synchronous channels
Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous
channels
Reserved
The WRDY flag in
are never set to 1.
The WRDY flag in
update period is elapsed, the PDC transfer request is never set to 1.
The WRDY flag in
are set to 1 as soon as the update period is elapsed.
The WRDY flag in
are set to 1 as soon as the selected comparison matches.
WRDY Flag and PDC Transfer Request
29
21
13
–
–
5
–
(2)
PTRM
“PWM Interrupt Status Register 2” on page 921
“PWM Interrupt Status Register 2” on page 921
“PWM Interrupt Status Register 2” on page 921
“PWM Interrupt Status Register 2” on page 921
28
20
12
–
–
4
–
SYNC3
27
19
11
–
–
–
3
Description
SYNC2
“PWM Write Protect Status Register” on
26
18
10
–
–
–
2
“PWM Sync Channels Update
and the PDC transfer request
is set to 1 as soon as the
and the PDC transfer request
and the PDC transfer request
SAM3U Series
SAM3U Series
SYNC1
25
17
–
9
–
1
UPDM
(1)
(2)
SYNC0
24
16
–
8
–
0
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