SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 357

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.7.3
25.8
Figure 25-3. Memory Connections for External Devices
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
External Memory Mapping
Interrupt
SMC
NCS[0] - NCS[3]
The SMC has an interrupt line connected to the Nested Vector Interrupt Controller (NVIC). Han-
dling the SMC interrupt requires programming the NVIC before configuring the SMC.
Table 25-3.
Table 25-4.
Note:
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address
up to 16 Mbytes of memory.
If the physical memory device connected on one chip select is smaller than 16 Mbytes, it wraps
around and appears to be repeated within this space. The SMC correctly handles any valid
access to the memory device within the page (see
A[23:0] is only significant for 8-bit memory, A[23:1] is used for 16-bit memory.
0x60000000-0x60FFFFFF
0x61000000-0x61FFFFFF
0x62000000-0x62FFFFFF
0x63000000-0x63FFFFFF
0x04000000-0x07FFFFFF
0x68000000-0x6FFFFFFF
Address
D[15:0]
A[23:0]
Instance
NWE
NRD
SMC
1. See
Peripheral IDs
External Memory Mapping
Section 25.16.2 ”NFC Control
ID
9
Use
Chip Select 0 (16 MB)
Chip Select 1
Chip Select 2
Chip Select 3
Undefined Area
NFC Command Registers
Registers”, i.e., CMD_ADDR description.
8 or 16
NCS0
NCS1
Figure
NCS2
Memory Enable
Output Enable
Write Enable
A[25:0]
D[15:0] or D[7:0]
NCS3
(1)
Memory Enable
).
Memory Enable
Memory Enable
SAM3U Series
SAM3U Series
Access
Read-write
Read-write
Read-write
Read-write
Read-write
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