SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 124

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.12.3
13.12.3.1
13.12.3.2
13.12.3.3
13.12.3.4
124
SAM3U Series
ASR, LSL, LSR, ROR, and RRX
Syntax
Operation
Restrictions
Condition flags
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with
Extend.
where:
op
S
result of the operation, see
Rd
Rm
Rs
significant byte is used and can be in the range 0 to 255.
n
MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0.
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of
places specified by constant n or register Rs.
RRX moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains
unchanged. For details on what result is generated by the different instructions, see
ations” on page
Do not use SP and do not use PC.
If S is specified:
• these instructions update the N and Z flags according to the result
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
ASR
LSL
LSR
ROR
ASR
LSL
LSR
ROR
is one of:
Arithmetic Shift Right.
Logical Shift Left.
Logical Shift Right.
Rotate Right.
is an optional suffix. If S is specified, the condition code flags are updated on the
is the destination register.
is the register holding the value to be shifted.
is the register holding the shift length to apply to the value in Rm. Only the least
is the shift length. The range of shift length depends on the instruction:
shift length from 1 to 32
shift length from 0 to 31
shift length from 1 to 32
shift length from 1 to 31.
95.
“Conditional execution” on page
98.
6430E–ATARM–29-Aug-11
“Shift Oper-