SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 831

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
h. Program LLI_W(n).DMAC_CTRLBx with the following field’s values:
i.
j.
k. Program the channel registers in the Memory for the second descriptor. This
l.
m. The LLI_B(n).DMAC_DADDRx is not relevant if previous word aligned descriptor
n. Program LLI_B(n).DMAC_CTRLAx with the following field’s values:
o. Program LLI_B(n).DMAC_CTRLBx with the following field’s values:
p. Program LLI_B(n).DMAC_CFGx memory location for channel x with the following
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC).
–DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
Program LLI_W(n).DMAC_CFGx register for channel x with the following field’s
values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Address are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
Program LLI_W(n).DMAC_DSCRx with the address of LLI_B(n) descriptor. And set
the DSCRx_IF to the AHB Layer ID. This operation actually links the Word oriented
descriptor on the second byte oriented descriptor. When block_length[1:0] is equal
to 0 (multiple of 4) LLI_W(n).DMAC_DSCRx points to 0, only LLI_W(n) is relevant.
descriptor will be byte oriented. This descriptor is referred to as LLI_B(n), standing
for LLI Byte oriented.
The LLI_B(n).DMAC_SADDRx field in memory must be set with the starting
address of the HSMCI_FIFO address.
was enabled. If 1, 2 or 3 bytes are transferred, that address is user defined and not
word aligned.
–DST_WIDTH is set to BYTE.
–SRC_WIDTH is set to BYTE.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer).
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
field’s values:
–FIFOCFG defines the watermark of the DMAC channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
DMA Controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
Next descriptor location points to 0.
DMA Controller is able to prefetch data and write HSMCI simultaneously.
SAM3U Series
SAM3U Series
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