SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 877

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

38.6.2.2
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
Comparator
The comparator continuously compares its counter value with the channel period defined by
CPRD in the
defined by CDTY in the
generate an output signal OCx accordingly.
The different properties of the waveform of the output OCx are:
• the clock selection. The channel counter is clocked by one of the clocks provided by the
• the waveform period. This channel parameter is defined in the CPRD field of the
• the waveform duty-cycle. This channel parameter is defined in the CDTY field of the
(
------------------------------------------ -
(
----------------------------------------------------- -
clock generator described in the previous section. This channel parameter is defined in the
CPRE field of the
reset at 0.
PWM_CPRDx register.
If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1,
2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
(
------------------------------- -
(
------------------------------------------ -
2
2
X
CRPD
duty cycle
duty cycle
×
×
×
MCK
X
CPRD
CPRD
MCK
MCK
×
MCK
×
CPRD
DIVA
“PWM Channel Period Register” on page 945
)
×
DIVA
=
=
)
)
(
----------------------------------------------------------------------------------------------------------- -
(
----------------------------------------------------------------------------------------------------------------------------- -
or
period 1
(
period
)
“PWM Channel Mode Register” on page 941
or
(
------------------------------------------ -
CRPD
“PWM Channel Duty Cycle Register” on page 943
(
----------------------------------------------------- -
2
–
×
⁄
MCK
CPRD
×
2
⁄
) 1
DIVB
MCK
fchannel_x_clock
–
×
period
⁄
(
)
period
DIVB
fchannel_x_clock
)
⁄
2
)
×
CDTY
×
CDTY
)
(PWM_CPRDx) and the duty-cycle
) )
(PWM_CMRx). This field is
SAM3U Series
SAM3U Series
(PWM_CDTYx) to
877
877