SAM3U1C Atmel Corporation, SAM3U1C Datasheet - Page 829

• Manufacturer Part Number: SAM3U1C
• Manufacturer: Atmel Corporation

Specifications of SAM3U1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

37.8.8
37.8.8.1
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
READ_MULTIPLE_BLOCK
Block Length is a Multiple of 4
10. Send The STOP_TRANSMISSION command writing HSMCI_ARG then
11. Wait for XFRDONE in HSMCI_SR register.
1. Wait until the current command execution has successfully terminated.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Set RDPROOF bit in HSMCI_MR to avoid overflow.
5. Program HSMCI_DMA register with the following fields:
6. Issue a READ_MULTIPLE_BLOCK command.
7. Program the DMA Controller to use a list of descriptors:
HSMCI_CMDR.
a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
– ROPT field is set to 0.
– OFFSET field is set to 0.
– CHKSIZE is user defined.
– DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMA transfer by
c. Program the channel registers in the Memory with the first descriptor. This descrip-
d. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting
e. The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.
f.
g. Program LLI_W(n).DMAC_CTRLBx with the following field’s values:
was previously set to false.
reading the DMAC_EBCISR register.
tor will be word oriented. This descriptor is referred to as LLI_W(n), standing for LLI
word oriented transfer for block n.
address of the HSMCI_FIFO address.
Program LLI_W(n).DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to WORD
–SRC_WIDTH is set to WORD
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4.
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC).
–DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
DMA Controller is able to prefetch data and write HSMCI simultaneously.
SAM3U Series
SAM3U Series
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