MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 107

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3.2.10
EDATAHI and EDATALO are the EEPROM data registers.
In normal modes, all EDATAHI and EDATALO bits read 0 and are not writable.
In special modes, all EDATAHI and EDATALO bits are readable and writable.
3.4
3.4.1
Write and read operations are both used for the program and erase algorithms described in this subsection.
These algorithms are controlled by a state machine whose timebase, EECLK, is derived from the oscillator
clock via a programmable divider. The command register as well as the associated address and data
registers operate as a buffer and a register (2-stage FIFO) so that a new command along with the necessary
data and address can be stored to the buffer while the previous command is remains in progress. The
pipelined operation allows a simplification of command launching. Buffer empty as well as command
completion are signalled by flags in the EEPROM status register. Interrupts for the EEPROM will be
generated if enabled.
The next four subsections describe:
3.4.1.1
Prior to issuing any program or erase command, it is first necessary to write the ECLKDIV register to
divide the oscillator down to within 150 kHz to 200 kHz range. The program and erase timings are also a
Freescale Semiconductor
Reset
Reset
•
•
•
•
W
W
R
R
How to write the ECLKDIV register.
Command write sequences used to program, erase, and verify the EEPROM memory.
Valid EEPROM commands.
Errors resulting from illegal EEPROM operations.
Functional Description
Program and Erase Operation
EEPROM Data Register (EDATA)
7
0
7
0
Writing the ECLKDIV Register
6
0
6
0
Figure 3-16. EEPROM Data Low Register (EDATALO)
Figure 3-15. EEPROM Data High Register (EDATAHI)
MC9S12HZ256 Data Sheet, Rev. 2.05
5
0
5
0
4
0
4
0
EDLO
EDHI
3
0
3
0
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
2
0
2
0
1
0
1
0
0
0
0
0
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