MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 52

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1 MC9S12HZ256 Device Overview
1.8.2.2
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
1.8.3
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.
After the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. After this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
1.9
Consult the respective block description chapter for information on the module behavior in stop, pseudo
stop, and wait mode.
1.10
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. Both local masking and CCR masking are included as listed in
be generated through external control of the RESET pin, through the clock and reset generator module
CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG
and VREG block description chapters for detailed information on reset generation.
1.10.1
Table 1-11
52
0xFFFC, 0xFFFD
0xFFFE, 0xFFFF
0xFFFA, 0xFFFB
0xFFF8, 0xFFF9
0xFFF6, 0xFFF7
0xFFF4, 0xFFF5
Vector Address
Low Power Modes
Resets and Interrupts
lists interrupt sources and vectors in default order of priority.
Unsecuring the Microcontroller
Vectors
Executing from External Memory
Voltage Reset (see CRG Flags Register to
External Reset, Power On Reset or Low
Unimplemented instruction trap
determine reset source)
Clock Monitor fail reset
Interrupt Source
COP failure reset
Table 1-11. Interrupt Vector Locations
MC9S12HZ256 Data Sheet, Rev. 2.05
XIRQ
SWI
Mask
None
None
None
None
None
CCR
X-Bit
COPCTL (CME, FCME)
COP rate select
Local Enable
Table
None
None
None
None
1-11. System resets can
Freescale Semiconductor
HPRIO Value
to Elevate
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