MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 126

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1.2
Read: Anytime. Write: Never; writes to these registers have no effect.
If the ATDDIEN1 bit of the associated I/O pin is set to 0 (digital input buffer is disabled), a read returns a
1. If the ATDDIEN1 bit of the associated I/O pin is set to 1 (digital input buffer is enabled), a read returns
the status of the associated pin.
4.3.1.3
Read: Anytime. Write: Anytime.
This register configures port pins PAD[7:0] as either input or output.
If a data direction bit is 0 (pin configured as input), then a read value on PTADx depends on the associated
ATDDIEN1 bit. If the associated ATDDIEN1 bit is set to 1 (digital input buffer is enabled), a read on
PTADx returns the value on port AD pin. If the associated ATDDIEN1 bit is set to 0 (digital input buffer
is disabled), a read on PTADx returns a 1.
126
DDRAD[7:0]
Reset
Reset
Field
7:0
W
W
R
R
DDRAD7
PTIAD7
Data Direction Port AD
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port AD Input Register (PTIAD)
Port AD Data Direction Register (DDRAD)
1
0
7
7
= Reserved or Unimplemented
DDRAD6
PTIAD6
1
0
6
6
Figure 4-4. Port AD Data Direction Register (DDRAD)
Figure 4-3. Port AD Input Register (PTIAD)
Table 4-3. DDRAD Field Descriptions
DDRAD5
PTIAD5
MC9S12HZ256 Data Sheet, Rev. 2.05
1
0
5
5
DDRAD4
PTIAD4
1
0
4
4
Description
DDRAD3
PTIAD3
1
0
3
3
DDRAD2
PTIAD2
1
0
2
2
DDRAD1
PTIAD1
Freescale Semiconductor
1
0
1
1
DDRAD0
PTIAD0
1
0
0
0