MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 110

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.4.1.2
The EEPROM command controller is used to supervise the command write sequence to execute program,
erase, mass erase, sector modify, and erase verify operations. Before starting a command write sequence,
it is necessary to check that there is no pending access error or protection violation (the ACCERR and
PVIOL flags must be cleared in the ESTAT register).
After this initial step, the CBEIF flag must be tested to ensure that the address, data and command buffers
are empty. If so, the command sequence can be started. The following 3-step command write sequence
must be strictly adhered to and no intermediate access to the EEPROM array is permitted between the 3
steps. It is possible to read any EEPROM register during a command sequence. The command write
sequence is as follows:
The completion of the command is indicated by the CCIF flag setting. The CCIF flag only sets when all
active and pending commands have been completed.
The EEPROM command controller will flag errors in command write sequences by means of the
ACCERR (access error) and PVIOL (protection violation) flags in the ESTAT register. An erroneous
command write sequence will abort and set the appropriate flag. If set, the user must clear the ACCERR
or PVIOL flags before commencing another command write sequence. By writing a 0 to the CBEIF flag
the command sequence can be aborted after the word write to the EEPROM address space or after writing
a command to the ECMD register and before the command is launched. Writing a 0 to the CBEIF flag in
this way will set the ACCERR flag.
A summary of the launching of a program operation is shown in
writes the appropriate command to the ECMD register.
110
1. Write an aligned word to be to a valid EEPROM array address. The address and data will be stored
2. Write a valid command, listed in
3. Clear the CBEIF flag by writing a 1 to CBEIF to launch the command. When the CBEIF flag is
in internal buffers.
— For program and sector modify, all address and data bits are valid.
— For erase, the value of the data bytes are ignored.
— For mass erase and erase verify, the address can be anywhere in the available address space of
— For sector erase, the address bits[1:0] are ignored.
cleared, the CCIF flag is cleared by hardware indicating that the command was successfully
launched. The CBEIF flag will be set again indicating the address, data, and command buffers are
ready for a new command write sequence to begin.
the array.
Command Write Sequence
MC9S12HZ256 Data Sheet, Rev. 2.05
Table
3-10, to the ECMD register.
Figure
3-18. For other operations, the user
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