MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 519

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

sub-block, the type of breakpoint used determines if BDM becomes active before or after execution of the
next instruction.
In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses
0xFF00 to 0xFFFF. BDM registers are mapped to addresses 0xFF00 to 0xFF07. The BDM uses these
registers which are readable anytime by the BDM. However, these registers are not readable by user
programs.
18.4.3
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode. Target system memory includes all memory that is accessible by the CPU such
as on-chip RAM, EEPROM, FLASH EEPROM, I/O and control registers, and all external memory.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to
be in active BDM for execution, although they can continue to be executed in this mode. When executing
a hardware command, the BDM sub-block waits for a free CPU bus cycle so that the background access
does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the
CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the
operation does not intrude on normal CPU operation provided that it can be completed in a single cycle.
However, if an operation requires multiple cycles the CPU is frozen until the operation is complete, even
though the BDM found a free cycle.
Freescale Semiconductor
BDM Hardware Commands
If an attempt is made to activate BDM before being enabled, the CPU
resumes normal instruction execution after a brief delay. If BDM is not
enabled, any hardware BACKGROUND commands issued are ignored by
the BDM and the CPU is not delayed.
MC9S12HZ256 Data Sheet, Rev. 2.05
NOTE
Chapter 18 Background Debug Module (BDMV4)
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