MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 529

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 18-13
occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Because this is
not a probable situation, the protocol does not prevent this conflict from happening.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE
BDM commands. This provides backwards compatibility with the existing POD devices which are not
able to execute the hardware handshake protocol. It also allows for new POD devices, that support the
hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
Freescale Semiconductor
(TARGET MCU)
BKGD PIN
DRIVES SYNC
TARGET MCU
TO BKGD PIN
BDM CLOCK
DRIVES TO
BKGD PIN
BKGD PIN
HOST
shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
This information is being provided so that the MCU integrator will be aware
that such a conflict could eventually occur.
READ_BYTE
HOST
Figure 18-12. ACK Abort Procedure at the Command Level
AND STARTS TO EXECUTES
READ_BYTE CMD IS ABORTED
Figure 18-13. ACK Pulse and SYNC Request Conflict
THE READ_BYTE CMD
MEMORY ADDRESS
TARGET
BY THE SYNC REQUEST
HOST SYNC REQUEST PULSE
BDM DECODE
ACK PULSE
16 CYCLES
(OUT OF SCALE)
MC9S12HZ256 Data Sheet, Rev. 2.05
HOST AND
TARGET DRIVE
TO BKGD PIN
AT LEAST 128 CYCLES
NOTE
ELECTRICAL CONFLICT
HIGH-IMPEDANCE
HOST
SYNC RESPONSE
FROM THE TARGET
(OUT OF SCALE)
READ_STATUS
TARGET
Chapter 18 Background Debug Module (BDMV4)
NEW BDM COMMAND
NEW BDM COMMAND
HOST
SPEEDUP PULSE
TARGET
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