MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 139

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.4.2
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
4.3.4.3
Read: Anytime. Write: Anytime.
This register configures port pins PP[5:0] as either input or output.
If a PWM channel is enabled, the corresponding pin is forced to be an output and the associated Data
Direction Register bit has no effect. Channel 5 can also force the corresponding pin to be an input if the
shutdown feature is enabled.
When the IIC bus is enabled, the PP[5:4] pins become the SCL and SDA bidirectional pins respectively
as long as the corresponding PWM channels are disabled. The associated Data Direction Register bits have
no effect.
When the SCI1 transmitter is enabled, the PP[0] pin becomes the TXD1 output pin and the associated Data
Direction Register bit has no effect. When the SCI1 receiver is enabled, the PP[2] pin becomes the RXD1
input pin and the associated Data Direction Register bit has no effect.
If the PWM, IIC and SCI1 functions are disabled, the corresponding Data Direction Register bit reverts to
control the I/O direction of the associated pin.
Freescale Semiconductor
DDRP[5:0]
Reset
Reset
Field
5:0
W
W
R
R
Data Direction Port P
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port P Input Register (PTIP)
Port P Data Direction Register (DDRP)
0
0
0
0
7
7
= Reserved or Unimplemented
= Reserved or Unimplemented
0
0
0
0
6
6
Figure 4-25. Port P Data Direction Register (DDRP)
Figure 4-24. Port P I/O Register (PTP)
Table 4-18. DDRP Field Descriptions
DDRP5
PTIP5
MC9S12HZ256 Data Sheet, Rev. 2.05
u
0
5
5
DDRP4
PTIP4
u
0
4
4
Description
u = Unaffected by reset
DDRP3
PTIP3
u
0
3
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
DDRP2
PTIP2
u
0
2
2
DDRP1
PTIP1
u
0
1
1
DDRP0
PTIP0
u
0
0
0
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