MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 505

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.2
The following paragraphs describe, in address order, all the VREG3V3 registers and their individual bits.
17.3.2.1
The VREGCTRL register allows to separately enable features of VREG3V3.
17.4
Block VREG3V3 is a voltage regulator as depicted in
the regulator core (REG), a low-voltage detect module (LVD), a power-on reset module (POR) and a
low-voltage reset module (LVR). There is also the regulator control block (CTRL) which represents the
interface to the digital core logic but also manages the operating modes of VREG3V3.
17.4.1
VREG3V3, respectively its regulator core has two parallel, independent regulation loops (REG1 and
REG2) that differ only in the amount of current that can be sourced to the connected loads. Therefore, only
REG1 providing the supply at V
Freescale Semiconductor
Reset
LVDS
Field
LVIE
LVIF
2
1
0
W
R
Functional Description
Register Descriptions
REG — Regulator Core
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V
1 Input voltage V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
VREG3V3 — Control Register (VREGCTRL)
0
0
7
On entering the Reduced Power Mode the LVIF is not cleared by the
VREG3V3.
= Unimplemented or Reserved
Figure 17-2. VREG3V3 — Control Register (VREGCTRL)
0
0
6
DDA
DDA
is above level V
is below level V
DD
Table 17-3. MCCTL1 Field Descriptions
/V
MC9S12HZ256 Data Sheet, Rev. 2.05
SS
0
0
5
is explained. The principle is also valid for REG2.
LVIA
LVID
and FPM.
or RPM or shutdown mode.
NOTE
0
0
4
Description
Figure
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
17-1. The regulator functional elements are
0
0
3
LVDS
0
2
LVIE
0
1
LVIF
0
0
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