MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 202

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Clocks and Reset Generator (CRGV4)
5.6
The interrupts/reset vectors requested by the CRG are listed in
chapter for related vector addresses and priorities.
5.6.1
The CRG generates a real-time interrupt when the selected interrupt time period elapses. RTI interrupts
are locally disabled by setting the RTIE bit to 0. The real-time interrupt flag (RTIF) is set to 1 when a
timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
The RTI continues to run during pseudo-stop mode if the PRE bit is set to 1. This feature can be used for
periodic wakeup from pseudo-stop if the RTI interrupt is enabled.
5.6.2
The CRG generates a PLL lock interrupt when the LOCK condition of the PLL has changed, either from
a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the
LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
5.6.3
The CRG generates a self-clock mode interrupt when the SCM condition of the system has changed, either
entered or exited self-clock mode. SCM conditions can only change if the self-clock mode enable bit
(SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power-on reset (POR)
or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure. For details
on the clock quality check refer to
(CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1).
SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set
to 1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
202
Interrupts
Real-Time Interrupt
PLL Lock Interrupt
Self-Clock Mode Interrupt
Real-time interrupt
Interrupt Source
LOCK interrupt
SCM interrupt
Section 5.4.4, “Clock Quality
Table 5-15. CRG Interrupt Vectors
MC9S12HZ256 Data Sheet, Rev. 2.05
Mask
CCR
I bit
I bit
I bit
CRGINT (LOCKIE)
CRGINT (SCMIE)
CRGINT (RTIE)
Local Enable
Table
Checker.” If the clock monitor is enabled
5-15. Refer to the device overview
Freescale Semiconductor