MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 507

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.5
This subsection describes how VREG3V3 controls the reset of the MCU.The reset values of registers and
signals are provided in
listed in
17.5.1
During chip power-up the digital core may not work if its supply voltage V
deassertion level (V
kept high until V
continues the start-up sequence. The power-on reset is active in all operation modes of VREG3V3.
17.5.2
For details on low-voltage reset see
17.6
This subsection describes all interrupts originated by VREG3V3.
The interrupt vectors requested by VREG3V3 are listed in
priorities are defined at MCU level.
17.6.1
In FPM VREG3V3 monitors the input voltage V
bit LVDS is set to 1. Vice versa, LVDS is reset to 0 when V
indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit
LVIE = 1.
Freescale Semiconductor
Table
Resets
Interrupts
Power-On Reset
Low-Voltage Reset
LVI — Low-Voltage Interrupt
Low Voltage Interrupt (LVI)
17-4.
On entering the Reduced Power Mode, the LVIF is not cleared by the
VREG3V3.
Power-on reset
Low-voltage reset
DD
PORD
Interrupt Source
exceeds V
Reset Source
Section 17.3, “Memory Map and Register
). Therefore, signal POR which forces the other blocks of the device into reset is
PORD
Table 17-5. VREG3V3 — Interrupt Vectors
Table 17-4. VREG3V3 — Reset Sources
Section 17.4.6, “LVR — Low-Voltage
. Then POR becomes low and the reset generator of the device
MC9S12HZ256 Data Sheet, Rev. 2.05
Always active
Available only in Full Performance Mode
LVIE = 1; Available only in Full Performance Mode
DDA
NOTE
. Whenever V
Local Enable
Table
DDA
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
Local Enable
rises above level V
17-5. Vector addresses and interrupt
DDA
Definition”. Possible reset sources are
drops below level V
DD
Reset”.
is below the POR
LVID
. An interrupt,
LVIA
the status
507