MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 178

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.8
This register selects the timeout period for the real-time interrupt.
Read: anytime
Write: anytime
178
RTR[6:4]
RTR[3:0]
Reset
SCME
Field
Field
PRE
PCE
6:4
3:0
2
1
0
W
R
RTI Enable during Pseudo-Stop Bit — PRE enables the RTI during pseudo-stop mode. Write anytime.
0 RTI stops running during pseudo-stop mode.
1 RTI continues running during pseudo-stop mode.
Note: If the PRE bit is cleared the RTI dividers will go static while pseudo-stop mode is active. The RTI dividers
COP Enable during Pseudo-Stop Bit — PCE enables the COP during pseudo-stop mode. Write anytime.
0 COP stops running during pseudo-stop mode
1 COP continues running during pseudo-stop mode
Note: If the PCE bit is cleared the COP dividers will go static while pseudo-stop mode is active. The COP dividers
Self-Clock Mode Enable Bit — Normal modes: Write once —Special modes: Write anytime — SCME can not
be cleared while operating in self-clock mode (SCM=1).
0 Detection of crystal clock failure causes clock monitor reset (see
1 Detection of crystal clock failure forces the MCU in self-clock mode (see
Real-Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See
Real-Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.
source clock for the RTI is OSCCLK.
CRG RTI Control Register (RTICTL)
0
0
7
A write to this register initializes the RTI counter.
will not initialize like in wait mode with RTIWAI bit set.
will not initialize like in wait mode with COPWAI bit set.
= Unimplemented or Reserved
RTR6
0
6
Table 5-5. PLLCTL Field Descriptions (continued)
Figure 5-11. CRG RTI Control Register (RTICTL)
Table 5-6. RTICTL Field Descriptions
RTR5
MC9S12HZ256 Data Sheet, Rev. 2.05
Table 5-7
0
5
shows all possible divide values selectable by the RTICTL register. The
RTR4
NOTE
0
4
Description
Description
RTR3
0
3
Section 5.5.1, “Clock Monitor
RTR2
0
2
Section 5.4.7.2, “Self-Clock
Freescale Semiconductor
RTR1
0
1
Reset”).
Table
RTR0
Mode”).
0
0
5-7.