MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 249

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4
This section provides a complete functional description of the LCD32F4B block, detailing the operation
of the design from the end user perspective in a number of subsections.
8.4.1
8.4.1.1
During a reset the following conditions exist:
8.4.1.2
The frequency of the oscillator clock (OSCCLK) and divider determine the LCD clock frequency. The
divider is set by the LCD clock prescaler bits, LCLK[2:0], in the LCD control register 0 (LCDCR0).
Table 8-7
8 MHz, 4 MHz, 2 MHz, 1 MHz, and 0.5 MHz.
For other combinations of OSCCLK and divider not shown in
used to calculate the LCD frame frequency for each multiplex mode:
The possible divider values are shown in
Freescale Semiconductor
OSCCLK = 16.0
OSCCLK = 0.5
OSCCLK = 1.0
OSCCLK = 2.0
OSCCLK = 4.0
OSCCLK = 8.0
Frequency in
Oscillator
•
•
MHz
The LCD32F4B system is configured in the default mode, 1/4 duty and 1/3 bias, that means all
backplanes are used.
All frontplane enable bits, FP[31:0]EN are cleared and the ON/OFF control for the display, the
LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high
impedance state. The MCU pin state during reset is defined by the port integration module (PIM).
Functional Description
shows the LCD clock and frame frequency for some multiplexed mode at OSCCLK = 16 MHz,
LCD Driver Description
Frontplane, Backplane, and LCD System During Reset
LCD Clock and Frame Frequency
LCLK2
LCD Clock Prescaler
0
0
0
0
0
0
0
1
1
1
1
1
LCD Frame Frequency (Hz)
LCLK1
0
0
0
1
1
1
1
0
0
0
1
1
Table 8-7. LCD Clock and Frame Frequency
LCLK0
MC9S12HZ256 Data Sheet, Rev. 2.05
0
1
1
0
0
1
1
0
0
1
0
1
Table
Divider
131072
16384
16384
32768
65536
1024
2048
2048
4096
4096
8192
8192
8-7.
Frequency [Hz]
LCD Clock
=
488
244
488
244
488
244
488
244
488
244
244
122
OSCCLK (Hz)
----------------------------------- -
Divider
Table
Chapter 8 Liquid Crystal Display (LCD32F4BV1)
1/1 Duty
8-7, the following formula may be
488
244
488
244
488
244
488
244
488
244
244
122
Frame Frequency [Hz]
Duty
1/2 Duty
244
122
244
122
244
122
244
122
244
122
122
61
1/3 Duty
163
163
163
163
163
81
81
81
81
81
81
40
1/4 Duty
122
122
122
122
122
61
61
61
61
61
61
31
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