MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 340

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
8
9
10
12.3.2.2
The CANCTL1 register provides various control bits and handshake status information of the MSCAN
module as described below.
Read: Anytime
Write: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal and
anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and
INITAK = 1).
340
Not including WUPE, INITRQ, and SLPRQ.
TSTAT1 and TSTAT0 are not affected by initialization mode.
RSTAT1 and RSTAT0 are not affected by initialization mode.
CLKSRC
LOOPB
LISTEN
WUPM
CANE
Field
7
6
5
4
2
MSCAN Enable
0 MSCAN module is disabled
1 MSCAN module is enabled
MSCAN Clock Source — This bit defines the clock source for the MSCAN module (only for systems with a clock
generation module;
0 MSCAN clock source is the oscillator clock
1 MSCAN clock source is the bus clock
Loopback Self Test Mode — When this bit is set, the MSCAN performs an internal loopback which can be used
for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN
input pin is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does
normally when transmitting and treats its own transmitted message as a message received from a remote node.
In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure
proper reception of its own message. Both transmit and receive interrupts are generated.
0 Loopback self test disabled
1 Loopback self test enabled
Listen Only Mode — This bit configures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN
messages with matching ID are received, but no acknowledgement or error frames are sent out (see
Section 12.4.5.4, “Listen-Only
applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any
messages when listen only mode is active.
0 Normal operation
1 Listen only mode activated
Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is
applied to protect the MSCAN from spurious wake-up (see
0 MSCAN wakes up the CPU after any recessive to dominant edge on the CAN bus
1 MSCAN wakes up the CPU only in case of a dominant pulse on the CAN bus that has a length of T
MSCAN Control Register 1 (CANCTL1)
Table 12-4. CANCTL1 Register Field Descriptions
Section 12.4.3.2, “Clock
MC9S12HZ256 Data Sheet, Rev. 2.05
Mode”). In addition, the error counters are frozen. Listen only mode supports
System,” and
Description
Section Figure 12-40., “MSCAN Clocking
Section 12.4.6.4, “MSCAN Sleep
Freescale Semiconductor
Mode”).
Scheme,”).
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