MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 273

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Whenever FAST = 0 only 16-bit write accesses to the duty cycle registers are allowed, 8-bit write accesses
can lead to unpredictable duty cycles.
While fast mode is enabled (FAST = 1), 8-bit write accesses to the high byte of the duty cycle registers are
allowed, because only the high byte of the duty cycle register is used to determine the duty cycle.
The following sequence should be used to update the current magnitude and direction for coil 0 and coil
1 of the motor to achieve consistent PWM output:
At the next timer counter overflow, the duty cycle registers will be copied to the working duty cycle
registers. Sequential writes to the duty cycle register x will result in the previous data being overwritten.
9.4.1.1.2
In full H-bridge mode, the PWM channels x and x + 1 operate independently. The duty cycle working
registers are updated whenever a timer counter overflow occurs.
9.4.1.1.3
In half H-bridge mode, the PWM channels x and x + 1 operate independently. In this mode, each PWM
channel can be configured such that one pin is released and the other pin is a PWM output.
shows a typical configuration in half H-bridge mode.
The two pins associated with each channel are switchable between released mode and PWM output
dependent upon the state of the MCOM[1:0] bits in the MCCCx (channel control) register. See register
description in
state of the S bit has no effect.
Freescale Semiconductor
1. Write to duty cycle register x
2. Write to duty cycle register x + 1.
PWM Channel x + 1
PWM Channel x
Section 9.3.2.4, “Motor Controller Channel Control
Full H-Bridge Mode (MCOM = 10)
Half H-Bridge Mode (MCOM = 00 or 01)
Figure 9-10. Typical Dual Full H-Bridge Mode Configuration
MnC0P
MnC0M
MnC1P
MnC1M
MC9S12HZ256 Data Sheet, Rev. 2.05
Registers”. In half H-bridge mode, the
Chapter 9 Motor Controller (MC10B8CV1)
Motor n, Coil 0
Motor n, Coil 1
Figure 9-11
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