MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 157

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.8.2
Read: Anytime. Write: Never, writes to this register have no effect.
If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the
associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the
associated pin.
4.3.8.3
Read: Anytime. Write: Anytime.
This register configures port pins PV[7:0] as either input or output.
When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the
associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the
corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Freescale Semiconductor
DDRV[7:0]
Reset
Reset
Field
7:0
W
W
R
R
DDRV7
PTIV7
Data Direction Port V
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port V Input Register (PTIV)
Port V Data Direction Register (DDRV)
u
0
7
7
= Reserved or Unimplemented
DDRV6
PTIV6
u
0
6
6
Figure 4-51. Port V Data Direction Register (DDRV)
Figure 4-50. Port V Input Register (PTIV)
Table 4-36. DDRV Field Descriptions
DDRV5
PTIV5
MC9S12HZ256 Data Sheet, Rev. 2.05
u
0
5
5
DDRV4
PTIV4
u
0
4
4
Description
u = Unaffected by reset
DDRV3
PTIV3
u
0
3
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
DDRV2
PTIV2
u
0
2
2
DDRV1
PTIV1
u
0
1
1
DDRV0
PTIV0
u
0
0
0
157